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march 2010 rev 6 1/47 1 m25p128 128-mbit, low-voltage, serial flash memory with 54-mhz spi bus interface features ? 128-mbit flash memory ? 2.7 to 3.6 v single supply voltage ? spi bus compatible serial interface ? 54 mhz clock rate (maximum) for 65 nm devices ? v pp = 9 v for fast program/erase mode (optional) ? page program (up to 256 bytes): ? in 0.5 ms (typical) for 65 nm devices ? in 0.4 ms (typical with v pp = 9 v) for 65 nm devices ? sector erase (2 mbit) ? bulk erase (128 mbit) ? electronic signature ? jedec standard two-byte signature (2018h) ? more than 10,000 erase/program cycles per sector ? more than 20-year data retention ? rohs compliant packages vdfpn8 (me) 8 x 6 mm (mlp8) so16 (mf) 300 mils width www.numonyx.com
contents m25p128 2/47 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 chip select (s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 hold (hold ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 write protect/enhanced program supply voltage (w /v pp ) . . . . . . . . . . . . . 9 2.7 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 sector erase and bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 12 4.4 fast program/erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.8 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3 read identification (rdid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.4 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.1 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
m25p128 contents 3/47 6.4.2 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.3 bp2, bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.4 srwd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.5 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.6 read data bytes (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.7 read data bytes at higher speed (fast_read) . . . . . . . . . . . . . . . . . . . 27 6.8 page program (pp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.9 sector erase (se) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.10 bulk erase (be) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
list of tables m25p128 4/47 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. read identification (rdid) data -out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7. protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. power-up timing and vwi threshold for 65 nm device s . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 9. power-up timing and vwi threshold for 130 nm devi ces . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 10. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 11. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 12. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 13. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 14. dc characteristics for 65 nm devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 table 15. ac characteristics for 65 nm devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 table 16. dc characteristics for 130 nm devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 17. ac characteristics for 130 nm devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 18. vdfpn8 (mlp8), 8-lead very thin dual flat package no lead, 8 6mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 19. so16 wide ? 16 lead plastic small outline, 300 mils body width . . . . . . . . . . . . . . . . . . . . 44 table 20. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 21. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
m25p128 list of figures 5/47 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. vdfpn connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. so connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. write enable (wren) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. write disable (wrdi) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. read identificati on (rdid) instruction sequence and data-o ut sequence . . . . . . . . . . . . . 21 figure 11. read status register (rdsr) instruction sequence and data-out sequence . . . . . . . . . . . 23 figure 12. write status register (wrsr) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 13. read data bytes (read) instruction sequence and data-out sequence . . . . . . . . . . . . . . 26 figure 14. read data bytes at higher speed (fast _read) instruction and data-out sequence . . . . 27 figure 15. page program (pp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 16. sector erase (se) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 figure 17. bulk erase (be) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 18. power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 19. ac measurement i/o wa veform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 20. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 21. write protect setup and hold timing during wrsr when srwd =1. . . . . . . . . . . . . . . . . . 41 figure 22. hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 23. output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 24. v pph timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 25. vdfpn8 (mlp8), 8-lead very thin dual flat package no lead, 8x6mm, package outline . 43 figure 26. so16 wide ? 16 lead plastic small outline, 300 mils body width . . . . . . . . . . . . . . . . . . . . 44
description m25p128 6/47 1 description the m25p128 is a 128-mbit (16 mbit 8) serial flash memory, with advanced write protection mechanisms and accessed by a hi gh speed spi-compatible bus, which allows clock frequency operation up to 54 mhz (1) . the memory can be programmed 1 to 256 bytes at a time, using the page program instruction. the memory is organized as 64 sectors, each containing 1024 pages. each page is 256 bytes wide. thus, the whole memory can be vi ewed as consisting of 65536 pages, or 16777216 bytes. an enhanced fast program/erase mode is av ailable to speed up operations in factory environment. the device enters this mode whenever the v pph voltage is applied to the write protect/enhanced program supply voltage pin (w /v pp ). the whole memory can be erased using the bulk erase instruction, or a sector at a time, using the sector erase instruction. in order to meet environmental requirements, numonyx offers these devices in lead-free and rohs compliant packages. note: important: this datasheet details the func tionality of the m25p128 devices, based on the previous 130 nm mlc process or based on the current 65 nm slc process, identified by the process identification digit ?a? in the device marking and process letter "b" in the part number. the new device is backward compatible with the old one. figure 1. logic diagram 1. 54 mhz operation is available only fo r 65 nm process technology devices, which are identified by the process identification digit ?a? in t he device marking and process letter "b" in the part number. ai11313b s v cc m25p128 hold v ss w/v pp q c d
m25p128 description 7/47 figure 2. vdfpn connections 1. there is an exposed die paddle on the underside of th e mlp8 package. this is pulled, internally, to v ss , and must not be allowed to be connected to any other voltage or signal line on the pcb. 2. see package mechanical section for package dimensions , and how to identify pin-1. figure 3. so connections 1. du = don?t use 2. see package mechanical section for package dimensions , and how to identify pin-1. table 1. signal names symbol description direction c serial clock input d serial data input input q serial data output output s chip select input w /v pp write protect/enhanced program supply voltage input hold hold input v cc supply voltage supply v ss ground ground 1 ai11314b 2 3 4 8 7 6 5 d v ss c hold q sv cc m25p128 w/v pp 1 ai11315b 2 3 4 16 15 14 13 du du du du v cc hold du du m25p128 5 6 7 8 12 11 10 9 q v ss du du s d c w/v pp
signal description m25p128 8/47 2 signal description 2.1 serial data output (q) this output signal is used to transfer data seria lly out of the device. data is shifted out on the falling edge of serial clock (c). 2.2 serial data input (d) this input signal is used to transfer data seri ally into the device. it receives instructions, addresses, and the data to be programmed. values are latched on the rising edge of serial clock (c). 2.3 serial clock (c) this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edg e of serial clock (c). 2.4 chip select (s ) when this input signal is high, the device is dese lected and serial data output (q) is at high impedance. unless an internal program, erase or write status register cycle is in progress, the device will be in the standby power mode. driving chip select (s ) low selects the device, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. 2.5 hold (hold ) the hold (hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be sele cted, with chip select (s ) driven low.
m25p128 signal description 9/47 2.6 write protect/enhanced program supply voltage (w /v pp ) w /v pp is both a control input and a power supply pin. the two functions are selected by the voltage range applied to the pin. if the w /v pp input is kept in a low voltage range (0v to v cc ) the pin is seen as a control input. this input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as spec ified by the values in the bp2, bp1 and bp0 bits of the status register). if v pp is in the range of v pph it acts as an additional power supply pin. in this case v pp must be stable until the program/erase algorithm is completed. 2.7 v cc supply voltage v cc is the supply voltage. 2.8 v ss ground v ss is the reference for the v cc supply voltage.
spi modes m25p128 10/47 3 spi modes these devices can be driven by a microcontrolle r with its spi peripheral running in either of the two following modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from t he falling edge of serial clock (c). the difference between the two modes, as shown in figure 5 , is the clock polarity when the bus master is in stand-by mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1) figure 4. bus master and memory devices on the spi bus 1. the write protect (w /v pp ) and hold (hold ) signals should be driven, hi gh or low as appropriate. 2. these pull-up resistors, r, ensure that the memory dev ices are not selected if the bus master leaves the s line in the high- impedance state. as the bus master may enter a state where a ll inputs/outputs are in high impedance at the same time (e.g.: when the bus master is reset), the clock line (c) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, s is pulled high while c is pulled low (thus ensuring that s and c do not become high at the same time, and so, that the t shch requirement is met). ai12836 spi bus master spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) hold hold hold r (2) r (2) r (2) v c c v cc v cc v cc v s s v ss v ss v ss r (2) w/v pp w/v pp w/v pp
m25p128 spi modes 11/47 figure 5. spi modes supported ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
operating features m25p128 12/47 4 operating features 4.1 page programming to program one data byte, two instructions are required: write enab le (wren), which is one byte, and a page program (pp) sequence, wh ich consists of four bytes plus data. this is followed by the internal program cycle (of duration t pp ). to spread this overhead, the page program (pp) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (pp) sequences with each containing only a few bytes (see section 6.8: page program (pp) , table 15: ac characteri stics for 65 nm devices , and table 17: ac characteristics for 130 nm devices ). 4.2 sector erase and bulk erase the page program (pp) instruction allows bits to be reset from 1 to 0. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be achieved either a sector at a time, using the se ctor erase (se) instruction, or throughout the entire memory, using the bulk erase (be) instruction. this starts an internal erase cycle (of duration t se or t be ). the erase instruction must be preceded by a write enable (wren) instruction. 4.3 polling during a write, program or erase cycle a further improvement in the time to write status register (wrsr), program (pp) or erase (se or be) can be achieved by not waiting for the worst case delay (t w , t pp , t se , or t be ). the write in progress (wip) bit is provided in the status register so that the application program can monitor its value, polling it to establish wh en the previous write cy cle, program cycle or erase cycle is complete. 4.4 fast program/erase mode the fast program/erase mode is used to speed up programming/erasing. the device enters the fast program/erase mode during th e page program, sector erase or bulk erase instruction whenever a voltage equal to v pph is applied to the w /v pp pin. the use of the fast program/er ase mode requires specific operating conditions in addition to the normal ones (v cc must be within the normal operating range): ? the voltage applied to the w /v pp pin must be equal to v pph (see table 11 ) ? ambient temperature, t a must be 25 c 10 c, ? the cumulated time during which w /v pp is at v pph should be less than 80 hours
m25p128 operating features 13/47 4.5 active power and standby power modes when chip select (s ) is low, the device is selected, and in the active power mode. when chip select (s ) is high, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). the device then goes in to the standby power mode. the device consumption drops to i cc1 . 4.6 status register the status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. see section 6.4: read status register (rdsr) for a detailed description of t he status register bits. 4.7 protection modes the environments where non-volatile memory devices are used can be very noisy. no spi device can operate correctly in the presence of excessive noise. to help combat this, the m25p128 features the following data protection mechanisms: ? power on reset and an internal timer (t puw ) can provide protection against inadvertent changes while the power supply is outside the oper ating specification. ? program, erase and write status register inst ructions are checked that they consist of a number of clock pulses that is a multip le of eight, before they are accepted for execution. ? all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ?power-up ? write disable (wrdi) instruction completion ? write status register (w rsr) instruction completion ? page program (pp) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion ? the block protect (bp2, bp1, bp0) bits allow part of the memory to be configured as read-only. this is the software protected mode (spm). ? the write protect (w /v pp ) signal allows the block prot ect (bp2, bp1, bp0) bits and status register write disable (srwd) bit to be protected. this is the hardware protected mode (hpm).
operating features m25p128 14/47 4.8 hold condition the hold (hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. however, taking this signal low does not terminate any write status register, program or erase cycle that is currently in progress. to enter the hold condition, the device must be selected, with chip select (s ) low. the hold condition starts on th e falling edge of the hold (hold ) signal, provided that this coincides with serial clock (c) being low (as shown in figure 6 ). the hold condition ends on the rising edge of the hold (hold ) signal, provided that this coincides with serial clock (c) being low. if the falling edge does not coincide with serial clock (c) being low, the hold condition starts after serial clock (c) next goes low. similarly, if the rising edge does not coincide with serial clock (c) being low, the hold cond ition ends after serial clock (c) next goes low. (this is shown in figure 6 ). during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. normally, the device is kept selected, with chip select (s ) driven low, for the whole duration of the hold conditio n. this is to ensure that the state of the internal logic remains unchanged from the moment of entering the hold condition. if chip select (s ) goes high while the device is in the ho ld condition, this has the effect of resetting the internal logic of the device. to restart communication with the device, it is necessary to drive hold (hold ) high, and then to drive chip select (s ) low. this prevents the device from going back to the hold condition. table 2. protected area sizes status register content memory content bp2 bit bp1 bit bp0 bit protected area unprotected area 0 0 0 none all sectors (sectors 0 to 63) (1) 1. the device is ready to accept a bulk erase instruction if, and only if, all block protect (bp2, bp1, bp0) are 0. 0 0 1 upper 64th (1 sector, 2mb) sectors 0 to 62 0 1 0 upper 32nd (2 sectors, 4mb) sectors 0 to 61 0 1 1 upper 16nd (4 sectors, 8mb) sectors 0 to 59 1 0 0 upper 8nd (8 sectors, 16mb) sectors 0 to 55 1 0 1 upper quarter (16 sectors, 32mb) lower 3 quarters (sectors 0 to 47) 1 1 0 upper half (32 sectors, 64mb) lower half (sectors 0 to 31) 1 1 1 all sectors (64 sectors, 128mb) none
m25p128 operating features 15/47 figure 6. hold condition activation ai02029d hold c hold condition (standard use) hold condition (non-standard use)
memory organization m25p128 16/47 5 memory organization the memory is organized as: ? 16777216 bytes (8 bits each) ? 64 sectors (2 mbits, 262144 bytes each) ? 65536 pages (256 bytes each). each page can be individually programmed (bits are programmed from 1 to 0). the device is sector or bulk erasable (bits are erased from 0 to 1) but not page erasable. figure 7. block diagram ai11316b hold s control logic high voltage generator i/o shift register address register and counter 256 byte data buffer 256 bytes (page size) x decoder y decoder size of the read-only memory area c d q status register 00000h ffffffh 000ffh w/v pp
m25p128 memory organization 17/47 table 3. memory organization sector address range 63 fc0000h ffffffh 62 f80000h fbffffh 61 f40000h f7ffffh 60 f00000h f3ffffh 59 ec0000h efffffh 58 e80000h ebffffh 57 e40000h e7ffffh 56 e00000h e3ffffh 55 dc0000h dfffffh 54 d80000h dbffffh 53 d40000h d7ffffh 52 d00000h d3ffffh 51 cc0000h cfffffh 50 c80000h cbffffh 49 c40000h c7ffffh 48 c00000h c3ffffh 47 bc0000h bfffffh 46 b80000h bbffffh 45 b40000h b7ffffh 44 b00000h b3ffffh 43 ac0000h afffffh 42 a80000h abffffh 41 a40000h a7ffffh 40 a00000h a3ffffh 39 9c0000h 9fffffh 38 980000h 9bffffh 37 940000h 97ffffh 36 900000h 93ffffh 35 8c0000h 8fffffh 34 880000h 8bffffh 33 840000h 87ffffh 32 800000h 83ffffh 31 7c0000h 7fffffh 30 780000h 7bffffh 29 740000h 77ffffh
memory organization m25p128 18/47 28 700000h 73ffffh 27 6c0000h 6fffffh 26 680000h 6bffffh 25 640000h 67ffffh 24 600000h 63ffffh 23 5c0000h 5fffffh 22 580000h 5bffffh 21 540000h 57ffffh 20 500000h 53ffffh 19 4c0000h 4fffffh 18 480000h 4bffffh 17 440000h 47ffffh 16 400000h 43ffffh 15 3c0000h 3fffffh 14 380000h 3bffffh 13 340000h 37ffffh 12 300000h 33ffffh 11 2c0000h 2fffffh 10 280000h 2bffffh 9 240000h 27ffffh 8 200000h 23ffffh 7 1c0000h 1fffffh 6 180000h 1bffffh 5 140000h 17ffffh 4 100000h 13ffffh 3 0c0000h 0fffffh 2 080000h 0bffffh 1 040000h 07ffffh 0 000000h 03ffffh table 3. memory organization (continued) sector address range
m25p128 instructions 19/47 6 instructions all instructions, addresses and data are shifted in and out of the device , most significant bit first. serial data input (d) is sampled on the first risi ng edge of serial clock (c) after chip select (s ) is driven low. then, the one-byte instructi on code must be shifted in to the device, most significant bit first, on serial data input (d), each bit being latched on the rising edges of serial clock (c). the instruction set is listed in table 4 . every instruction sequence starts with a one- byte instruction code. depending on the instruction, this might be follo wed by address bytes, or by data bytes, or by both or none. in the case of a read data bytes (read), re ad data bytes at higher speed (fast_read), read status register (rdsr) or read identifi cation (rdid) instruct ion, the shifted-in instruction sequence is followed by a data-out sequence. chip select (s ) can be driven high after any bit of the data-out sequence is being shifted out. in the case of a page program (pp), sector erase (se), bulk erase (be), write status register (wrsr), write enable (wren) or write disable (wrdi), chip select (s ) must be driven high exactly at a byte boundary, other wise the instruction is rejected, and is not executed. that is, chip select (s ) must driven high when the number of clock pulses after chip select (s ) being driven low is an exact multiple of eight. all attempts to access the memory array during a write status register cycle, program cycle or erase cycle are ignor ed, and the internal write st atus register cycle, program cycle or erase cycle continues unaffected. table 4. instruction set instruction description one-byte instruction code address bytes dummy bytes data bytes wren write enable 0000 0110 06h 0 0 0 wrdi write disable 0000 0100 04h 0 0 0 rdid read identification 1001 1111 9fh 0 0 1 to 3 rdsr read status register 0000 0101 05h 0 0 1 to wrsr write status register 0000 0001 01h 0 0 1 read read data bytes 0000 0011 03h 3 0 1 to fast_read read data bytes at higher speed 0000 1011 0bh 3 1 1 to pp page program 0000 0010 02h 3 0 1 to 256 se sector erase 1101 1000 d8h 3 0 0 be bulk erase 1100 0111 c7h 0 0 0
instructions m25p128 20/47 6.1 write enable (wren) the write enable (wren) instruction ( figure 8 ) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page program (pp), sector erase (se), bulk erase ( be) and write status register (wrsr) instruction. the write enable (wren) instruction is entered by driving chip select (s ) low, sending the instruction code, and then driving chip select (s ) high. figure 8. write enable (wren) instruction sequence 6.2 write disable (wrdi) the write disable (wrdi) instruction ( figure 9 ) resets the write enable latch (wel) bit. the write disable (wrdi) instruction is entered by driving chip select (s ) low, sending the instruction code, and then driving chip select (s ) high. the write enable latch (wel) bit is reset under the fo llowing conditions: ? power-up ? write disable (wrdi) instruction completion ? write status register (wrs r) instruction completion ? page program (pp) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) in struction completion figure 9. write disable (wrdi) instruction sequence c d ai02281e s q 2 1 34567 high impedance 0 instruction c d ai03750d s q 2 1 34567 high impedance 0 instruction
m25p128 instructions 21/47 6.3 read identification (rdid) the read identification (rdid) instruction allo ws the 8-bit manufacturer identification to be read, followed by two bytes of device identi fication. the manufacturer identification is assigned by jedec, and has the value 20h for numonyx. the device identification is assigned by the device manufacturer, and indica tes the memory type in the first byte (20h), and the memory capacity of the device in the second byte (18h). any read identification (rdid) instruction while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the device is first selected by driving chip select (s ) low. then, the 8-bit instruction code for the instruction is shifted in. this is followed by the 24-bit device identification, stored in the memory, being shifted out on serial data ou tput (q), each bit being shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 10 . the read identification (rdid) instruction is terminated by driving chip select (s ) high at any time during data output. when chip select (s ) is driven high, the device is put in the standby powe r mode. once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions. figure 10. read identification (rdid) instruction sequence and data-out sequence table 5. read identification (rdid) data-out sequence manufacturer identification device identification memory type memory capacity 20h 20h 18h c d s 2 1 3456789101112131415 instruction 0 ai06809b q manufacturer identification high impedance msb 15 1413 3210 device identification msb 16 17 18 28 29 30 31
instructions m25p128 22/47 6.4 read status register (rdsr) the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, ev en while a program, erase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instructio n to the device. it is also possible to read the status register continuously, as shown in figure 11 . the status and control bits of th e status register are as follows: 6.4.1 wip bit the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. 6.4.2 wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the in ternal write enable latch is set, when set to 0 the internal write enable latch is reset and no write status register , program or erase instruction is accepted. 6.4.3 bp2, bp1, bp0 bits the block protect (bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and er ase instructions. these bits are written with the write status register (wrsr) instruction. when one or more of the block protect (bp2, bp1, bp0) bits is set to 1, the rele vant memory area (as defined in table 2 ) becomes protected against page program (pp) and sector erase (se) instructions. the block protect (bp2, bp1, bp0) bits can be written provided that the hardware protected mode has not been set. the bulk erase (be) instruction is executed if, and only if, all block protect (bp2, bp1, bp0) bits are 0. 6.4.4 srwd bit the status register write disable (srwd) bi t is operated in conjunction with the write protect (w /v pp ) signal. the status register write disable (srwd) bit and write protect (w /v pp ) signal allow the device to be put in the hardware protected mode (when the status register write disable (srwd) bit is set to 1, and write protect (w /v pp ) is driven low). in this mode, the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become table 6. status register format b7 b0 srwd 0 0 bp2 bp1 bp0 wel wip status register write protect block protect bits write enable latch bit write in progress bit
m25p128 instructions 23/47 read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. figure 11. read status register (rdsr) instruction sequence and data-out sequence c d s 2 1 3456789101112131415 instruction 0 ai02031e q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
instructions m25p128 24/47 6.5 write status register (wrsr) the write status register (wrsr) instruction allows new values to be written to the status register. before it can be accepted, a write enable (wren) instruct ion must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruct ion is entered by driving chip select (s ) low, followed by the instruction code and the data byte on serial data input (d). the instruction sequence is shown in figure 12 . the write status register (wrs r) instruction has no effect on b6, b5, b1 and b0 of the status register. b6 and b5 are always read as 0. chip select (s ) must be driven high after the eighth bi t of the data byte has been latched in. if not, the write status register (wrsr) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed write stat us register cycle (whose duration is t w ) is initiated. while the writ e status register cycle is in prog ress, the status register may still be read to check the value of the write in pr ogress (wip) bit. the wr ite in progress (wip) bit is 1 during the self-timed write status regi ster cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) instruction allows the user to change the values of the block protect (bp2, bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in table 2 . the write status register (w rsr) instruction also allows the user to set or reset the status register write disable (srwd) bit in accordance with the write protect (w /v pp ) signal. the status register write disable (srwd) bit and write protect (w /v pp ) signal allow the device to be put in the hardware protected mode (hpm). the write status register (wrs r) instruction is not executed once the hardware protected mode (hpm) is entered. the protection features of the device are summarized in table 7 when the status register write disable (srwd) bi t of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable table 7. protection modes w /v pp signal srwd bit mode write protection of the status register memory content protected area (1) 1. as defined by the values in the block protect (bp2 , bp1, bp0) bits of the status register, as shown in table 2: protected area sizes . unprotected area (1) 10 software protected (spm) status register is writable (if the wren instruction has set the wel bit) the values in the srwd, bp2, bp1 and bp0 bits can be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions 00 11 01 hardware protected (hpm) status register is hardware write protected the values in the srwd, bp2, bp1 and bp0 bits cannot be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions
m25p128 instructions 25/47 latch (wel) bit has previously been set by a write enable (wren) in struction, regardless of the whether write protect (w /v pp ) is driven high or low. when the status register write disable (srwd) bi t of the status register is set to 1, two cases need to be considered, depending on the state of write protect (w /v pp ): ? if write protect (w /v pp ) is driven high, it is possible to write to the status register provided that the write enable latch (wel ) bit has previously been set by a write enable (wren) instruction. ? if write protect (w /v pp ) is driven low, it is not possible to write to the status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. (attempts to write to the status register are rejected, and are not accepted for execution). as a consequence, all the data bytes in the memory area that are software protected (spm) by the block protect (bp2, bp1, bp0) bits of the status register, are also hardware prot ected against data modification. regardless of the order of the two events, the hardware protected mode (hpm) can be entered: ? by setting the status regist er write disable (srwd) bit after driving write protect (w /v pp ) low ? or by driving write protect (w /v pp ) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protected mode (hpm) once entered is to pull write protect (w /v pp ) high. if write protect (w /v pp ) is permanently tied high, the ha rdware protected mode (hpm) can never be activated, and only the software protected mode (spm), us ing the block protect (bp2, bp1, bp0) bits of the status register, can be used. figure 12. write status register (wrsr) instruction sequence c d ai02282d s q 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
instructions m25p128 26/47 6.6 read data bytes (read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (c). the instruction sequence is shown in figure 13 . the first byte addressed can be at any locati on. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is terminated by driv ing chip select (s ) high. chip select (s ) can be driven high at any time during data output. any read data bytes (read) instruction, while an erase, pr ogram or write cycle is in prog ress, is rejected without having any effects on the cycle that is in progress. figure 13. read data bytes (read) instruction sequence and data-out sequence c d ai03748d s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2
m25p128 instructions 27/47 6.7 read data bytes at higher speed (fast_read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes at higher speed (fast_read) instruction is followed by a 3-byte address (a23- a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 14 . the first byte addressed can be at any locati on. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest address is re ached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes at higher speed (fast_ read) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data output. any read data bytes at higher speed (fast_read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 14. read data bytes at higher speed (fast_read) instruction and data-out sequence c d ai04006 s q 23 2 1 345678910 28293031 2221 3210 high impedance instruction 24 bit address 0 c d s q 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35
instructions m25p128 28/47 6.8 page program (pp) the page program (pp) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page program (pp) in struction is entered by driving chip select (s ) low, followed by the instruction code, three address bytes and at least one data byte on serial data input (d). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 15 . if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be prog rammed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (pp) sequences with each containing only a few bytes (see table 15: ac characteristics for 65 nm devices and table 17: ac characteristics for 130 nm devices ). chip select (s ) must be driven high after the eighth bi t of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (s ) is driven high, the self-tim ed page program cycle (whose duration is t pp ) is initiated. while the page program cyc le is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page progra m cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a pa ge which is protected by the block protect (bp2, bp1, bp0) bits (see table 2 and table 3 ) is not executed.
m25p128 instructions 29/47 figure 15. page program ( pp) instruction sequence c d ai04082b s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c d s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 765432 0 1 2072 msb msb msb msb msb
instructions m25p128 30/47 6.9 sector erase (se) the sector erase (se) instruction sets to 1 (ffh ) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instru ction must previously have been executed. after the write enable (wren) instruction ha s been decoded, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by drivin g chip select (s ) low, followed by the instruction code, and three address bytes on se rial data input (d). any address inside the sector (see table 3 ) is a valid address for the sector er ase (se) instruction. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 16 . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) inst ruction is not executed. as soon as chip select (s ) is driven high, the self-timed sector erase cycle (whose duration is t se ) is initiated. while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a sector erase (se) instructio n applied to a page which is protected by the block protect (bp2, bp1, bp0) bits (see table 2 and table 3 ) is not executed. figure 16. sector erase (se) instruction sequence 24 bit address c d ai03751d s 2 1 3456789 293031 instruction 0 23 22 2 0 1 msb
m25p128 instructions 31/47 6.10 bulk erase (be) the bulk erase (be) instruction sets all bits to 1 (ffh). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the bulk erase (be) instruction is entered by driving chip select (s ) low, followed by the instruction code on serial data input (d). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 17 . chip select (s ) must be driven high after the eighth bi t of the instruction code has been latched in, otherwise the bulk erase instructio n is not executed. as soon as chip select (s ) is driven high, the self-timed bulk erase cycle (whose duration is t be ) is initiate d. while the bulk erase cycle is in progress, the status re gister may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed bulk erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the bulk erase (be) instruction is executed only if all block protect (bp2, bp1, bp0) bits are 0. the bulk erase (be) instruction is ig nored if one, or more, sectors are protected. figure 17. bulk erase (be) instruction sequence c d ai03752d s 2 1 34567 0 instruction
power-up and power-down m25p128 32/47 7 power-up and power-down at power-up and power-down, the device must not be selected (that is chip select (s ) must follow the voltage applied on v cc ) until v cc reaches the correct value: ? v cc (min) at power-up, and then for a further delay of t vsl ? v ss at power-down usually a simple pull-up resi stor on chip select (s ) can be used to ensure safe and proper power-up and power-down. to avoid data corruption and inadvertent writ e operations during power-up, a power on reset (por) circuit is included. the logic inside the device is held reset while v cc is less than the power on reset (p or) threshold voltage, v wi ? all operations are disabled, and the device does not respond to any instruction. moreover, the device ignores all write enable (wren), page program (pp), sector erase (se), bulk erase (be) and write status regist er (wrsr) instructions until a time delay of t puw has elapsed after the moment that v cc rises above the v wi threshold. however, the correct operation of the device is not guaranteed if, by this time, v cc is still below v cc (min). no write status register, program or erase in structions should be sent until the later of: ? t puw after v cc passed the v wi threshold ? t vsl after v cc passed the v cc (min) level these values are specified in table 8 . if the delay, t vsl , has elapsed, after v cc has risen above v cc (min), the device can be selected for read instru ctions even if the t puw delay is not yet fully elapsed. at power-up, the device is in the following state: ? the device is in the standby power mode ? the write enable latch (wel) bit is reset. normal precautions must be taken for s upply rail decoupling, to stabilize the v cc supply. each device in a system should have the v cc rail decoupled by a suitable capacitor close to the package pins (generally, this capacitor is of the order of 0.1f). at power-down, when v cc drops from the operating voltage, to below the power on reset (por) threshold voltage, v wi , all operations are disabled and the device does not respond to any instruction. (the designer needs to be aware that if a power-down occurs while a write, program or erase cycle is in progress, some data corruption can result.) power up sequencing for fast program/erase mode: v cc should attain v ccmin before v pph is applied.
m25p128 initial deli very state 33/47 figure 18. power-up timing 8 initial delivery state the device is delivered with the memory arra y erased: all bits are set to 1 (each byte contains ffh). the status register contai ns 00h (all status register bits are 0). table 8. power-up timing and v wi threshold for 65 nm devices (1) 1. 65 nm technology devices are identif ied by the process identification digit ?a? in the device marking and process letter "b" in the part number. symbol parameter min. max. unit t vsl (2) 2. these parameters are characterized only. v cc (min) to s low 200 s t puw (2) time delay to write instruction 400 s v wi write inhibit voltage 1.5 2.5 v table 9. power-up timing and v wi threshold for 130 nm devices symbol parameter min. max. unit t vsl (1) 1. these parameters are characterized only. v cc (min) to s low 60 s t puw (2) time delay to write instruction 1 10 ms v wi write inhibit voltage 1.5 2.5 v v cc ai04009c v cc (min) v wi reset state of the device chip selection not allowed program, erase and write commands are rejected by the device tvsl tpuw time read access allowed device fully accessible v cc (max)
maximum rating m25p128 34/47 9 maximum rating stressing the device outside the ratings listed in table 10 may cause permanent damage to the device. these are stress ratings only, and o peration of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 10. absolute maximum ratings symbol parameter min. max. unit t stg storage temperature ?65 150 c v io input and output voltage (with respect to ground) ?0.5 v cc + 0.6 v v cc supply voltage ?0.2 4.0 v v pp fast program/erase voltage ?0.2 10.0 v v esd electrostatic discharge voltage (human body model) (1) 1. jedec std jesd22-a114a (c1=100 pf, r1=1500 , r2=500 ) ?2000 2000 v
m25p128 dc and ac parameters 35/47 10 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check th at the operating conditions in their circuit match the measurement conditions wh en relying on the quoted parameters. 1. output hi-z is defined as the point where data out is no longer driven. figure 19. ac measurement i/o waveform 1. sampled only, not 100% tested, at t a =25 c and a frequency of 20 mhz. table 11. operating conditions symbol parameter min. typ. max. unit v cc supply voltage 2.7 3.6 v v pph supply voltage on w /v pp pin for fast program/erase mode 8.5 9.5 v t a ambient operating temperature ?40 85 c t avpp ambient operating temperature for fast program/erase mode 15 25 35 c table 12. ac measurement conditions symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2v cc to 0.8v cc v input timing reference voltages 0.3v cc to 0.7v cc v output timing reference voltages v cc / 2 v table 13. capacitance symbol parameter test condition min. max. unit c out output capacitance (q) v out = 0v 8 pf c in input capacitance (other pins) v in = 0v 6 pf ai07455 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels 0.5v cc
dc and ac parameters m25p128 36/47 table 14. dc characteristics for 65 nm devices (1) 1. 65 nm process technology devices ar e identified by the proce ss identification digit ?a? in the device marking and process letter "b" in the part number. symbol parameter test condition (in addition to those in table 11 ) min. max. unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current s = v cc , v in = v ss or v cc 100 a i cc3 operating current (read) c=0.1v cc / 0.9.v cc at 54 mhz, q = open 6ma c=0.1v cc / 0.9.v cc at 33 mhz, q = open 4ma i cc4 operating current (pp) s = v cc 20 ma i cc5 operating current (wrsr) s = v cc 20 ma i cc6 operating current (se) s = v cc 20 ma i cc7 operating current (be) s = v cc 20 ma i ccpp (2) 2. characterized only. operating current for fast program/erase mode s = v cc , v pp = v pph 20 ma i pp (2) v pp operating current in fast program/erase mode s = v cc , v pp = v pph 20 ma v il input low voltage ? 0.5 0.3 v cc v v ih input high voltage 0.7 v cc v cc +0.4 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = ?100 av cc ?0.2 v table 15. ac characteristics for 65 nm devices (1) test conditions specified in table 11 and table 12 symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, pp, se, be, wren, wrdi, rdid, rdsr, wrsr d.c. 54 mhz f r clock frequency for read instructions d.c. 33 mhz t ch (2) t clh clock high time 9 ns t cl (2) t cll clock low time 9 ns t clch (3) clock rise time (4) (peak to peak) 0.1 v/ns t chcl (3) clock fall time (3) (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 4 ns t chsl s not active hold time (relative to c) 4 ns
m25p128 dc and ac parameters 37/47 t dvch t dsu data in setup time 2 ns t chdx t dh data in hold time 3 ns t chsh s active hold time (relative to c) 4 ns t shch s not active setup time (relative to c) 4 ns t shsl t csh s deselect time 50 ns t shqz (2) t dis output disable time 8 ns t clqv t v clock low to output valid 8 ns t clqx t ho output hold time 1 ns t hlch hold setup time (relative to c) 4 ns t chhh hold hold time (relative to c) 4 ns t hhch hold setup time (relative to c) 4 ns t chhl hold hold time (relative to c) 4 ns t hhqx (3) t lz hold to output low-z 8 ns t hlqz (3) t hz hold to output high-z 8 ns t whsl (5) write protect setup time 20 ns t shwl (5) write protect hold time 100 ns t vpphsl (3) (6) enhanced program supply voltage high to chip select low 200 ns t w write status register cycle time 1.3 15 s t pp (7) page program cycle time (256 bytes) 0.5 5ms page program cycle time (n bytes) int(n/8) x 0.015 (8) page program cycle time (v pp = v pph ) (256 bytes) 0.4 (3) t se sector erase cycle time 1.6 3 s t se sector erase cycle time (v pp = v pph )1.63s t be bulk erase cycle time 130 250 s t be bulk erase cycle time (v pp = v pph )120250s 1. 65 nm process technology devices are identified by the process identification digit ?a? in the device marking and process letter "b" in the part number. 2. t ch and t cl must be greater than or equal to 1/f c (max). 3. value is guaranteed by characteriza tion, not 100% tested in production. 4. expressed as a slew-rate. 5. only applicable as a constr aint for wrsr instruction when srwd is set to 1. 6. v pph should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is known. table 15. ac characteristics for 65 nm devices (1) (continued) test conditions specified in table 11 and table 12 symbol alt. parameter min. typ. max. unit
dc and ac parameters m25p128 38/47 7. when using the page program (pp) instruction to program consecutive byte s, optimized timings are obtained with one sequence including all the bytes vers us several sequences of only a few bytes. if only a single byte is programmed, the esti mated programming time is close to the time needed to program a full page of 256 bytes. therefore, it is highly recommended to use the page program (pp) instruction with a sequence of 256 consec utive bytes. (1 n 256) 8. int(a) corresponds to the upper integer part of a. for example int(12/8) = 2, int(32/8) = 4, int(15.3) = 16. table 16. dc characteristics for 130 nm devices symbol parameter test condition (in addition to those in table 11 ) min. max. unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current s = v cc , v in = v ss or v cc 100 a i cc3 operating current (read) c=0.1v cc / 0.9.v cc at 50mhz, q = open 8ma c=0.1v cc / 0.9.v cc at 20mhz, q = open 4ma i cc4 operating current (pp) s = v cc 20 ma i cc5 operating current (wrsr) s = v cc 20 ma i cc6 operating current (se) s = v cc 20 ma i cc7 operating current (be) s = v cc 20 ma i ccpp (1) 1. characterized only. operating current for fast program/erase mode s = v cc , v pp = v pph 20 ma i pp (2) v pp operating current in fast program/erase mode s = v cc , v pp = v pph 20 ma v il input low voltage ? 0.5 0.3v cc v v ih input high voltage 0.7v cc v cc +0.2 v v ol output low voltage i ol = 1.6ma 0.4 v v oh output high voltage ioh = ?100 av cc ?0.2 v
m25p128 dc and ac parameters 39/47 table 17. ac characteristics for 130 nm devices test conditions specified in table 11 and table 12 symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, pp, se, be, wren, wrdi, rdid, rdsr, wrsr d.c. 50 mhz f r clock frequency for read instructions d.c. 20 mhz t ch (1) t clh clock high time 9 ns t cl (1) t cll clock low time 9 ns t clch (2) clock rise time (3) (peak to peak) 0.1 v/ns t chcl (2) clock fall time (3) (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 5 ns t chsl s not active hold time (relative to c) 5 ns t dvch t dsu data in setup time 2 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 5 ns t shch s not active setup time (relative to c) 5 ns t shsl t csh s deselect time 100 ns t shqz (2) t dis output disable time 8 ns t clqv t v clock low to output valid 8 ns t clqx t ho output hold time 0 ns t hlch hold setup time (relative to c) 5 ns t chhh hold hold time (relative to c) 5 ns t hhch hold setup time (relative to c) 5 ns t chhl hold hold time (relative to c) 5 ns t hhqx (2) t lz hold to output low-z 8 ns t hlqz (2) t hz hold to output high-z 8 ns t whsl (4) write protect setup time 20 ns t shwl (4) write protect hold time 100 ns t vpphsl (2)(5) enhanced program supply voltage high to chip select low 200 ns t w write status register cycle time 5 15 ms t pp (6) page program cycle time (256 bytes) 2.5 7ms page program cycle time (n bytes) 2.5 page program cycle time (v pp = v pph ) (256 bytes) 1.2 (2) t se sector erase cycle time 2 6s sector erase cycle time (v pp = v pph )1.6 (2)
dc and ac parameters m25p128 40/47 figure 20. serial input timing t be bulk erase cycle time 105 250 s bulk erase cycle time (v pp = v pph )56 (2) 1. t ch and t cl must be greater than or equal to 1/f c (max). 2. value is guaranteed by characteriza tion, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constr aint for wrsr instruction when srwd is set to 1. 5. v pph should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is known. 6. when using the page program (pp) instruction to program consecutive byte s, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. if only a single byte is programmed, the esti mated programming time is close to the time needed to program a full page of 256 bytes. therefore, it is highly recommended to use the page program (pp) instruction with a sequence of 256 consec utive bytes. (1 n 256) table 17. ac characteristics for 130 nm devices (continued) test conditions specified in table 11 and table 12 symbol alt. parameter min. typ. max. unit c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl
m25p128 dc and ac parameters 41/47 figure 21. write protect setup and hold timing during wrsr when srwd =1 figure 22. hold timing c d s q high impedance twhsl tshwl ai07439 b w/v pp c q ai02032 s d hold tchhl thlch thhch tchhh thhqx thlqz
dc and ac parameters m25p128 42/47 figure 23. output timing figure 24. v pph timing c q ai01449e s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv s c d w/v pp v pph pp, se, be ai12092 tvpphsl end of pp, se or be (identified by wpi polling)
m25p128 package mechanical 43/47 11 package mechanical figure 25. vdfpn8 (mlp8), 8-lead very th in dual flat package no lead, 8x6mm, package outline 1. drawing is not to scale. 2. the circle in the top view of the package indicates the position of pin 1. table 18. vdfpn8 (mlp8), 8-lead very thin dual flat package no lead, 8 6mm, package mechanical data symbol millimeters inches typ. min. max. typ. min. max. a 0.85 1.00 0.0335 0.0394 a1 0.00 0.05 0.0000 0.0020 b 0.40 0.35 0.48 0.0157 0.0138 0.0189 d 8.00 0.3150 d2 5.16 (1) 1. d2 max should not exceed (d ? k ? 2 l). 0.2031 ddd 0.05 0.0020 e 6.00 0.2362 e2 4.80 0.1890 e1.27? ?0.0500? ? k 0.20 0.0079 l 0.50 0.45 0.60 0.0197 0.0177 0.0236 l1 0.15 0.0059 n8 8 d e vdfpn-02 a e e2 d2 l b l1 a1 ddd
package mechanical m25p128 44/47 figure 26. so16 wide ? 16 lead plasti c small outline, 300 mils body width 1. drawing is not to scale. table 19. so16 wide ? 16 l ead plastic small outline, 300 mils body width symbol millimeters inches typ min max typ min max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 10.10 10.50 0.398 0.413 e 7.40 7.60 0.291 0.299 e 1.27 ? ? 0.050 ? ? h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.40 1.27 0.016 0.050 0 8 0 8 ddd 0.10 0.004 e 16 d c h 1 8 9 so-h l a1 a ddd a2 b e h x 45?
m25p128 ordering information 45/47 12 ordering information for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact yo ur nearest numonyx sales office. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. table 20. ordering information scheme example: m25p128 ? v mf 6 t p b device type m25p = serial flash me mory for code storage device function 128 = 128 mbit (16 mbit 8) operating voltage v = v cc = 2.7 to 3.6 v package mf = so16 (300 mil width) me = vdfpn8 8 x 6 mm (mlp8) device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow option blank = standard packing t = tape and reel packing plating technology p or g = rohs compliant process technology blank = 130nm mlc b = 65 nm slc
revision history m25p128 46/47 13 revision history table 21. document revision history date revision changes 02-may-2005 0.1 first issue. 09-jun-2005 0.2 table 2: protected area sizes updated. memory capacity modified in section 6.3: read identification (rdid) . 28-aug-2005 0.3 updated t pp values in table 17: ac characteristics for 130 nm devices and t vsl value in table 8: power-up timing and vwi threshold for 65 nm devices . modified information in section 4.1: page programming and section 6.8: page program (pp) . 20-jan-2006 1 document status promoted from targ et specification to preliminary data. packages are ecopack? compliant. blank option removed under plating technology in table 20 . read electronic signature (res) instruction removed. i cc1 parameter updated in table 14: dc characteristics for 65 nm devices . 17-oct-2006 2 document status promot ed from preliminary data to full datasheet. write protect pin (w ) changed to write protect/enhanced program supply voltage (w/vpp) . section 4.4: fast program/erase mode and figure 24: vpph timing added. power-up specified for fast program/erase mode in power-up and power-down section. figure 4: bus master and memory devices on the spi bus modified and note 2 added. note 1 added below table 18: vdfpn8 (mlp8), 8-lead very thin dual flat package no lead, 8 6mm, package mechanical data . v io max modified in table 10: absolute maximum ratings . 10-dec-2007 3 applied numonyx branding. 26-nov-2009 4 removed references to multilevel cell technology and ecopack? packages. added: table 14: dc characteristics for 65 nm devices and table 15: ac characteristics for 65 nm devices , and references to 65 nm process technology throughout the document modified d2 value in table 18: vdfpn8 (mlp8), 8-lead very thin dual flat package no lead, 8 6mm, package mechanical data . 17-dec-2009 5 added ?process technology? to ordering information table. 1-feb-2010 6 added sector erase cycle times to table 15.: ac characteristics for 65 nm devices . changed icc3 test conditions in table 14.: dc characteristics for 65 nm devices as follows: 50 mhz to 54 mhz and 20 mhz to 33 mhz.
m25p128 47/47 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 2010, numonyx, b.v., all rights reserved.

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